A manufacturer of integrated circuits may often reduce overall manufacturing costs of its product by reducing the rejection rate for defective individual parts. One way to reduce the rejection rate is through ever finer refinement of manufacturing processes. Such refinement, though, is subject to the laws of diminishing returns. For example, a given integrated circuit may contain several thousand individual electronic components, such as transistors, diodes and the like. It may prove relatively easy and inexpensive to reduce the probability of a particular integrated circuit having one or more defective components to a certain percentage but increasingly difficult or expensive to improve the rejection rate beyond that point. Still, the presence of only one or two defective components out of thousands of components on an integrated circuit will dictate the rejection of that integrated circuit and potentially thousands of other integrated circuits.
Another solution to reducing the rejection rate, without expensive refinements of manufacturing processes, is to provide auxiliary, sometimes called redundant, circuit components on the integrated circuit. This solution is practical where testing can locate, within certain bounds, the defective component, and the circuit is readily reconfigurable to allow substitution of an auxiliary component for the defective component. Integrated circuit matrix memory arrays, including static random access memories (SRAM), are examples of such integrated circuits. In addition, many complex microprocessors now include significant amounts of on-chip memory, such as 64 kbytes or more of read-only memory and 64 kbytes or more of random access memory.
Memory arrays are characterized by the regular repetition of components. A very substantial portion of an integrated memory array is taken up by substantially identical memory cells disposed in regular rows and columns.
Decoding circuits are provided on the integrated circuit memory for operating on various combinations of electrical signals provided as inputs to the integrated circuit to generate signals within the integrated circuit for causing activation of a specific group of cells in the array. The decoder circuit generally includes a plurality of row decoders, each 0f which is adapted to provide a row select signal in response to a particular known set of electrical signals. Column decoders function similarly. A memory location is defined for each intersection of a row and a column.
The foregoing combinations of electrical signals typically comprise sets of logical signals. A logic signal is an electrical signal which represents two states, termed 0 and 1. Each logic signal represents a selected one of these states by being set at a certain predetermined voltage level, for example V.sub.cc for 1. Another voltage level may then be taken as 0 which is ground. Each logic signal represents one bit of information. While combinations of logic signals may be provided to integrated circuits in various ways, one common way, seen in digital computers, is to provide a separate conductive path for each logical signal. Different combinations, by virtue of activating different rows and columns of memory cells through the decoder, represent what are called memory addresses. The intersection of a particular row of cells or column of cells actuated is a memory element. Each row element is defined by the same number of logic signals. Similarly each column element is defined by the same number of logic signals.
A computer will address a memory address location in a time segment known as a memory cycle. Accordingly, one set of conductive paths, known as address lines, provides for transmission of all memory addresses. The set of address lines is referred to as the address bus. One memory address appears on the address bus in each memory cycle. Thus preserving timing of propagation of address signals is valuable.
The repetitive nature and "addressable" characteristics of integrated circuit array memories are the aspects of these integrated circuits which are exploited to substitute auxiliary elements. Because one row or column of memory cells is substantially like another row or column of memory cells, it does not matter which row or column stores any particular information. What matters is that it does store it and that the information can be located thereafter.
Substitution of auxiliary elements for regular elements requires reconfiguration of the circuit so that a memory address causes activation of a previously unused element of memory cells. It may also be necessary to cease activation of the defective regular element.
The electrically conductive paths supplying power to each row and column decoder, and the electrically conductive paths corresponding to the actuation lines, can be caused to lie on the surface of the integrated circuit and thus be accessible for reconfiguration.
Reconfiguration is achieved by incorporating an element, such as a fusible link, in a surface conductive path on the integrated circuit. Such fusible links, or configuration links, may be opened by a variety of steps, e.g., exposure to laser light to vaporize the link. Opening a link breaks the electrical connection between, for example, one element and the balance of the circuit. Opening a configuration link is used to remove a portion of a circuit element, or a substantial collection of elements, from the overall circuit.
In the prior art, reconfiguration has been done after evaluation of the addressable rows and columns in the memory, but without testing of the redundant elements. Obviously, the flaws which can occur in the regular portion of the memory array can also occur in the redundant elements. Once a memory circuit is reconfigured, or programmed, to substitute in a redundant location no further reconfiguration is possible to remove the redundant element should it prove defective.